An error correction code of CD is formed by interleaving 2-stage Reed-Solomon codes and referred to as CIRC (Cross Interleaved Reed-Solomon Code). The 2-stage Reed-Solomon codes used in the CIRC are referred to as C1, C2, respectively.
When error is corrected by the C1 code, for example, error-correction is carried out at the unit of 32 byte-data in which 4-byte parity data are added to 28-byte data. The 32-byte data are referred to as x.sub.0 to x.sub.31, respectively.
4-byte parity data are selected such that all of four equations on [Equation 1] yield "0"s: ##EQU1##
Data thus generated are recorded on the disc, and recorded data contains error due to various causes when reproduced.
Data (data containing errors) received by an error correction circuit after they had been read out from the disc are respectively referred to as x.sub.0 ' to x.sub.31 ' in order that they can be distinguished from data recorded on the disc.
When error correction is implemented in actual practice, data is received and then syndromes S0 to S3 are calculated based on [Equation 2]: ##EQU2##
Galois field theorem proved that there exists a finite field having 2.sup.8 elements. This finite field is expressed as GF(2.sup.8).
Codes used in the CD are defined by generator polynomial on [Equation 3]: EQU P(x)=x.sup.8 +x.sup.4 +x.sup.3 +x.sup.2 +1 (3)
Then, .alpha. is a root of equation established when P(x)=0.
Study of [Equation 2] reveals that, if received data contains no error, then S0=S1=S2=S3=0 (parity data are added for this reason). Conversely, if any one of syndromes were not "0", data error could be detected.
Although the syndrome should be calculated based on the [Equation 2] prior to the error correction, if the syndromes were calculated as described above, then the number of calculation would be increased.
Therefore, [Equation 2] is modified as [Equation 4]: ##EQU3##
The syndrome S1, for example, can be calculated in accordance with an algorithm shown in FIG. 3. Other syndromes S0, S2, S3 also can similarly be calculated by changing a predetermined power of .alpha. variously.
This calculation can be implemented by a circuit composed of an adder 41 supplied at one input thereof with received data, a register 42 for storing added data from the adder 41 and a multiply-by-power .alpha. circuit 43 for multiplying data stored in the register 42 with power .alpha. and supplying multiplied data to the other input of the adder 41 as shown in FIG. 4.
In FIG. 4, received data are input to the circuit in the sequential order from the data x.sub.31 ' under the condition that the register 42 is reset. Then, the value that was generated from the register 42 when the data x.sub.0 ' is input becomes the value of the syndrome S1.
Because the syndromes S0, S2, S3 are required in actual practice, as shown in FIG. 5, the syndromes are calculated by four registers 42.sub.0 to 42.sub.3.
The multiply-by-power .alpha. circuit 43 and the adder 41 can easily be realized by a combination of exclusive-OR (EX-OR) gates based on features of Galois field as shown in FIGS. 6 and 7.
It is important to detect an error amount prior to the error correction. Also, up to 2-byte error can be corrected in the code used by the CD.
Heretofore, calculation for determining an error amount (0- byte, 1-byte and 2-byte or larger) is carried out after calculation of the syndromes was finished.
If the received data x.sub.i ' is erroneous by an error amount e.sub.i ', then the syndromes expressed by [Equation 5] are to be calculated as will easily be understood from the parity data structure. ##EQU4##
The error amount e.sub.i and an erroneous received data location i are calculated from the syndromes thus calculated.
Since the four equations of [Equation 5] has two unknowns, these equations can be solved with ease, e.g., based on [Equation 6]: ##EQU5##
However, if received data had 2-byte error or greater, the received data would be corrected erroneously. Therefore, e.sup.i .alpha..sup.2i and e.sub.i .alpha..sup.3i should be calculated by using .alpha..sup.i and e.sub.i obtained from [Equation 5]. Then, it is necessary to confirm whether or not the calculated results are agreed with the syndromes S2, S3 of [Equation 5].
As described above, the conventional error correction circuit based on the above-mentioned algorithm should carry out at least one division and two multiplications when 1-byte error is corrected.
These calculations are those that are carried out on the Galois field. Since it is customary that, when the multiplication and the division are carried out on the Galois field, number to be calculated is modified in the form of power of .alpha., it is necessary to use a ROM in which a table of exponents and a table of logarithms for such modification are stored. Moreover, a peripheral circuit becomes complex in circuit arrangement and a circuit scale is unavoidably increased.